1. Field of the Invention
The present invention generally relates to scan chains used in testing integrated circuits and more particularly to a method and apparatus for preventing a race condition in a scan chain.
2. Background of the Invention
Scan chains are sometimes embedded in integrated circuit chips to facilitate testing of the chips prior to their delivery to a customer. A scan chain is a set of flip-flops connected in-a serial fashion. To test an integrated circuit by means of a scan chain, a pattern of data is serially clocked into the chain of flip-flops. On the first clock pulse of a series of clock pulses, the first flip-flop in the chain accepts a data bit; that is, a bit of data moves from the input to the output of the flip-flop. Since the output of the first flip-flop is the input of the second flip-flop, the first bit of data is then present at the input of the second flip-flop. At the second clock pulse, the data bit that was at the input of the second flip-flop moves to the output of that flip-flop and the first flip-flop accepts a new bit of data. Data continues to move in this manner through the chain of flip-flops until the first bit of data reaches the last flip-flop. This serial input of data into a scan chain is known as the shift mode.
After the shift mode is complete, the scan chain can enter the capture mode. In capture mode, the data bits at the outputs of the flip-flops are moved in parallel fashion into the logic circuits of the integrated circuit chip. The logic circuits then manipulate the data and the resulting data is moved in parallel fashion back to the flip-flops. A shift mode is then re-entered and the data is shifted out of the flip-flops one bit at a time in a manner similar to the way data was shifted in. The data that is shifted out of the flip-flops can be compared to the data that was shifted in to determine if the integrated circuit logic performed as expected in manipulating the data.
An undesirable situation known as a race condition can occur when data is serially clocked into a scan chain during shift mode. That is, due to the different path lengths the clock signal must traverse to reach the different flip-flops in a scan chain, a clock pulse may not reach a flip-flop in time for the pulse to cause the correct data bit to be passed from the input to the output of the flip-flop. A first bit of data at the input of a flip-flop could be overwritten by a second bit of data if the second bit arrives at the input of the flip-flop before the arrival of the clock pulse that is intended to move the first bit from the input to the output of the flip-flop. This would cause the second bit rather than the first bit to be passed from the input to the output of the flip-flop, a possibly undesirable result.
For example, if two bits of data that can be labeled A and B are to be shifted into a scan chain consisting of two flip-flops, a desired outcome of the shift mode might be that bit A is at the output of the second flip-flop and bit B is at the output of the first flip-flop. On the first clock pulse, bit A is moved from the input to the output of the first flip-flop. Bit A is then immediately available at the input of the second flip-flop. If no race condition exists, the next clock pulse will reach both flip-flops simultaneously. Bit A will then be moved from the input to the output of the second flip-flop and bit B will be moved from the input to the output of the first flip-flop. This results in the desired state of bit A at the output of the second flip-flop and bit B at the output of the first flip-flop. However, if a race condition does exist, the second clock pulse might not reach the second flip-flop until a significant time after it has reached the first flip-flop. In this case, the second clock pulse might cause bit B to pass from the input of the first flip-flop to the output of the first flip-flop and on to the input of the second flip-flop before the second clock pulse reaches the second flip-flop. If this happens, bit B will overwrite bit A at the input of the second flip-flop and will be waiting at the input of the second flip-flop for the second clock pulse. When the second clock pulse reaches the second flip-flop, bit B will pass from the input to the output of the second flip-flop. At the end of two clock cycles, then, bit B will be present at the outputs of both flip-flops. These values at the outputs of the flip-flops do not correspond to the desired outcome.